The trajectory of semiconductor evolution is heading toward atomic scales. According to the latest roadmap from Imec, the industry is targeting 0.3nm process nodes by 2038. This goal represents a fundamental shift in how transistor density is achieved and measured.

Redefining Moore's Law

Imec suggests that the traditional interpretation of Moore's Law—focused on individual transistor shrinkage—is no longer sufficient. Instead, the focus is shifting toward overall logic cell area (the product of Cell Height and CPP). As the Contacted Poly Pitch (CPP) begins to stagnate, density gains must come from optimizing cell height and architectural efficiency.

The Rise of CFET Architecture

A critical transition is expected by 2033 with the A7 node (approximately 0.7nm), where Complementary FET (CFET) transistors become viable. Unlike current designs that place n-type and p-type transistors side-by-side, CFETs stack them vertically. This 3D integration removes the traditional n-p separation from the cell height, potentially reducing area by up to 20% and extending scaling capabilities.

Key Milestones toward 0.3nm

The roadmap outlines several aggressive targets. By 2028, the A14 class (1.4nm) is expected to enter operation, with CPP dropping to 45nm and cell height reaching 115nm. By the 2033 A7 generation, cell height is projected to drop further to roughly 80nm, utilizing a 4.5-track standard-cell architecture.

Advanced Materials and Memory

To enable these breakthroughs, Imec is researching 2D TMD materials to optimize channel lengths and reduce contact resistance. Additionally, the company is advancing ferroelectric memory research (both capacitors and FETs) to support low-voltage operations and high-density integration, which are critical for the next generation of AI hardware.