Micron has presented its roadmap for DRAM, HBM and NAND, aiming at memory that must sustain the growth in demand driven by artificial intelligence. At its core is the 1δ production node, described as the company's fifth consecutive leadership node, with its ramp expected in the second half of 2027 in Boise, Idaho.

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Two memories built on this node stand out for the market. DDR6, aimed at servers and designed for high-reliability applications, promises more than double the bandwidth of DDR5. Micron positions itself as lead partner for key customers in adopting the new generation, and is also targeting a 1 TB RDIMM module as its highest-capacity product for the industry.

Micron’s DDR6 Doubles DDR5 Bandwidth While LPDDR6 Delivers 35% Better Power Efficiency, Both Built O

Image: Micron

LPDDR6 is meant for both data centers and mobile devices. According to the company, it consumes 35% less power than LPDDR5, with an even larger advantage at some densities. Micron worked with Meta to explain how LPDDR6's new features make it suitable for data centers too, a sign that energy efficiency has become central for large cloud operators.

From flat to vertical

The roadmap also looks beyond the planar model. Micron is investing in research to move DRAM and NAND toward three-dimensional designs, shifting growth from surface to height. For DRAM, the company has chosen to focus on the 6F2 cell, abandoning 4F2, which it considers to have no viable scaling path. Development of 3D DRAM will begin soon after the first High-NA EUV products.

In HBM, Micron plans vHBM, with memory stacked directly on the processor: the first generation is expected around 2028, the third around 2030. Alongside it is vEIM, vertical memory for edge AI inference, targeting about 2 TB/s of bandwidth and less than 1 pJ per bit.

Micron’s DDR6 Doubles DDR5 Bandwidth While LPDDR6 Delivers 35% Better Power Efficiency, Both Built O

Image: Micron

The most delicate part concerns how these chips connect to the rest of the infrastructure. Micron points to hybrid bonding as the answer to interconnect density: bringing contacts ever closer is the only way to raise bandwidth, but the technique still needs time before it can be deployed in high volume. The company says its capability here is strong.

In NAND, Micron has presented its G11 generation with more than 400 layers, a figure reported by a single source and still to be confirmed by the company in production details. Overall, the strategy aims to cover working memory, storage and AI accelerators at once, trying to meet a demand that Micron says is growing faster than any previous cycle.

The memories announced are still in development, so their arrival on the market depends on the next industrial steps.